package ffte.core.mixed

import spinal.core._
import spinal.lib._

import ffte.types.VecComplex
import ffte.property.{getFFTIW,getFFTOW}
import ffte.algorithm.FFTGen.{msbFFT}

/**
 * Mixed Space Block (MSB) FFT implementation
 *
 * This class implements FFT using the Mixed-Space Block decomposition method
 * with mixed architecture (combining flat and streamed implementations).
 * The MSB method is based on the Cooley-Tukey algorithm and requires
 * twiddle factor multiplication between stages.
 *
 * Mixed MSB Architecture:
 * - First stage: Uses flat or streamed implementation based on rgen flag
 * - Twiddle rotation: Complex multiplication with configurable twiddle factors
 * - Second stage: Uses opposite architecture from first stage
 * - Cooley-Tukey decomposition for any composite transform size
 *
 * Key Features:
 * - Twiddle factor multiplication using specialized rotator component
 * - Mixed architecture selection for optimal resource/performance balance
 * - Supports any composite transform size (not limited to coprime factors)
 * - Streaming connection through rotator for pipeline efficiency
 *
 * @tparam T Mixed method type parameter
 * @param S Scaling shift amount for fixed-point overflow prevention
 * @param p MSB decomposition structure containing stage and twiddle information
 */
class msb[T <: Mixed](val S: Int, val p: msbFFT[T]) extends mixedComponents[T] {

    /**
     * Twiddle factor rotator component
     *
     * Implements the complex multiplication with twiddle factors required
     * by the Cooley-Tukey decomposition. The rotator handles the
     * W_N^(k*n1*n2) terms that appear between the two FFT stages.
     *
     * Configuration:
     * - Width: interW (intermediate precision between stages)
     * - Permutation tables: From MSB decomposition for proper index mapping
     * - Rgen flag: Controls rotator architecture optimization
     */
    val r = new rotator(interW, p.p.first.store_tab, p.p.second.load_tab, p.p.rgen)

    /**
     * First stage to rotator connection
     *
     * Routes the first stage FFT output to the twiddle factor rotator.
     * The rotator applies the necessary phase rotations required
     * by the Cooley-Tukey decomposition.
     */
    f_block.u.io.q >> r.io.d

    /**
     * Rotator to second stage connection
     *
     * Routes the rotated intermediate results from the rotator
     * to the second stage FFT processor input.
     */
    r.io.q >> s_block.u.io.d

    /**
     * Input connection to first stage
     *
     * Routes the streaming input to the first stage FFT processor.
     * The first stage architecture (flat vs streamed) is determined
     * by the rgen flag in the mixedComponents trait.
     */
    io.d >> f_block.u.io.d

    /**
     * Output connection from second stage
     *
     * Routes the second stage output to the component output.
     * The second stage uses the opposite architecture from
     * the first stage for balanced performance.
     */
    io.q << s_block.u.io.q

    /**
     * Total component delay in clock cycles
     *
     * The total delay includes:
     * - First stage FFT delay (f_block.delay)
     * - Second stage FFT delay (s_block.delay)
     * - Rotator delay for twiddle factor multiplication (r.delay)
     *
     * @return Total delay from input to output in clock cycles
     */
    def delay = f_block.delay + s_block.delay + r.delay
}
